cy29946 2.5 v or 3.3 v, 200-mhz, 1:10 clock distribution buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07286 rev. *g revised may 11, 2011 2.5 v or 3.3 v, 200-mhz, 1:10 clock distribution buffer features 2.5 v or 3.3 v operation 200-mhz clock support two lvcmos-/lvttl-compatible inputs ten clock outputs: drive up to 20 clock lines 1 or 1/2 configurable outputs output three-state control 250-ps max output-to-output skew pin-compatible with mpc946, mpc9446 available in commercial and industrial temperature range 32-pin tqfp package description the cy29946 is a low-voltage 200-mhz clock distribution buffer with the capability to select one of two lvcmos/lvttl compatible input clocks. thes e clock sources can be used to provide for test clocks as well as the primary system clocks. all other control inputs are lvcmos/lvttl compatible. the 10 outputs are lvcmos or lvttl compatible and can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. the cy29946 is capable of generating 1 and 1/2 signals from a 1 source. these signals are generated and retimed internally to ensure minimal skew between the 1 and 1/2 signals. sel(a:c) inputs allow flexibility in selecting the ratio of 1 to1/2 outputs. the cy29946 outputs can also be three-stated via mr/oe# input. when mr/oe# is set high, it resets the internal flip-flops and three-states the outputs. block diagram 0 1 /1 /2 r 0 1 /1 /2 r 0 1 /1 /2 r 3 3 4 qa0:2 qb0:2 qc0:3 dsela dselb dselc mr/oe# tclk1 tclk0 tclk_sel [+] feedback
cy29946 document #: 38-07286 rev. *g page 2 of 9 cy29946 mr/oe# vss qa0 vddc qa1 vss qa2 vddc vddc qc0 vss qc1 vddc qc2 vss qc3 vss qb0 vddc qb1 vss qb2 vddc vddc tclk_sel vdd tclk0 tclk1 dsela dselb dselc vss 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 pin configuration pin description [1] pin name pwr i/o description 3, 4 tclk(0,1) i, pu external reference/test clock input 26, 28, 30 qa(2:0) vddc o clock outputs 19, 21, 23 qb(2:0) vddc o clock outputs 10, 12, 14, 16 qc(0:3) vddc o clock outputs 5, 6, 7 dsel(a:c) i, pd divider select inputs . when high, selects ? 2 input divider. when low, selects ? 1 input divider. 1 tclk_sel i, pd tclk select input . when low, tclk0 clock is selected and when high tclk1 is selected. 32 mr/oe# i, pd output enable input . when asserted low, the outputs are enabled and when asserted high, internal flip-flops are reset and the outputs are three-stated. if more than 1 bank is being used in /2 mode, a reset must be performed (mr/oe# asserted high) after power-up to ensure all internal flip-flops are set to the same state. 9, 13, 17, 18, 22, 25, 29 vddc 2.5 v or 3.3 v power supply for output clock buffers 2 vdd 2.5 v or 3.3 v power supply 8, 11, 15, 20, 24, 27, 31 vss common ground note 1. pd = internal pull-down. pu = internal pull-up. [+] feedback
cy29946 document #: 38-07286 rev. *g page 3 of 9 absolute maximum conditions [2] maximum input voltage relative to v ss ............. v ss ? 0.3 v maximum input voltage relative to v dd ............. v dd + 0.3 v storage temperature ..... ............ ............... ?65 ? c to +150 ? c operating temperature............................... ?40 ? c to +85 ? c maximum esd protection............................................... 2 kv maximum power supply................................................ 5.5 v maximum input current ............. .............. .............. .... 20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc electrical specifications v dd = v ddc = 3.3 v 10% or 2.5 v 5%, over the specified temperature range parameter description conditions min typ max unit v il input low voltage v ss ?0.8v v ih input high voltage 2.0 ? v dd v i il input low current [3] ? ? ?100 a i ih input high current [3] ? ? 100 a v ol output low voltage [4] i ol = 20 ma ? ? 0.4 v v oh output high voltage [4] i oh = ?20 ma, v dd = 3.3 v 2.5 ? ? v i oh = ?20 ma, v dd = 2.5 v 1.8 ? ? i ddq quiescent supply current ? 5 7 ma i dd dynamic supply current v dd = 3.3 v, outputs @ 100 mhz, cl = 30 pf ? 130 ? ma v dd = 3.3 v, outputs @ 160 mhz, cl = 30 pf ? 225 ? v dd = 2.5 v, outputs @ 100 mhz, cl = 30 pf ? 95 ? v dd = 2.5 v, outputs @ 160 mhz, cl = 30 pf ? 160 ? z out output impedance v dd = 3.3 v 12 15 18 w v dd = 2.5 v 14 18 22 c in input capacitance ? 4 ? pf notes 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 3. inputs have pull-up/pull-down resistors that effect input current. 4. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines. [+] feedback
cy29946 document #: 38-07286 rev. *g page 4 of 9 ac electrical specifications v dd = v ddc = 3.3 v 10% or 2.5 v 5%, over the specified temperature range [5] parameter description conditions min typ max unit f max input frequency [6] v dd = 3.3 v ? ? 200 mhz v dd = 2.5 v ? ? 170 t pd ttl_clk to q delay [6] 5.0 ? 11.5 ns f outdc output duty cycle [6, 7] measured at v dd /2 45?55% t pzl , t pzh output enable time (all outputs) 2 ? 10 ns t plz , t phz output disable time (all outputs) 2 ? 10 ns t skew output-to-output skew [6, 8] ? 150 250 ps t skew(pp) part-to-part skew [9] ?2.04.5ns t r /t f output clocks rise/fall time [8] 0.8 v to 2.0 v, v dd = 3.3 v 0.10 ? 1.0 ns 0.6 v to 1.8 v, v dd = 2.5 v 0.10 ? 1.3 notes 5. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. 6. outputs driving 50 ? transmission lines. 7. 50% input duty cycle. 8. see figure 1 on page 5 . 9. part-to-part skew at a given temperature and voltage. [+] feedback
cy29946 document #: 38-07286 rev. *g page 5 of 9 pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm cy29946 dut figure 1. lvcmos_clk cy29946 test reference for v cc = 3.3 v and v cc = 2.5 v t pd lvcmos_clk q vcc gnd vcc /2 vcc gnd vcc /2 figure 2. lvcmos propagation delay (t pd ) test reference vcc gnd vcc /2 t p t0 dc = tp / t0 x 100% figure 3. outp ut duty cycle (f outdc ) figure 4. output-to-output skew t sk(0) t sk(0) vcc gnd vcc /2 vcc gnd vcc /2 [+] feedback
cy29946 document #: 38-07286 rev. *g page 6 of 9 package drawing and dimensions figure 5. 32-pin tqfp 7 7 1.0 mm a3210 ordering information part number package type production flow cy29946axc 32-pin tqfp commercial, 0 ? c to +70 ? c cy29946axct 32-pin tqfp ? tape and reel commercial, 0 ? c to +70 ? c cy29946axi 32-pin tqfp industrial, ?40 ? c to +85 ? c CY29946AXIT 32-pin tqfp ? tape and reel industrial, ?40 ? c to +85 ? c ordering code definitions t = tape and reel; blank = tube temperature range: x = c or i c = commercial; i = industrial pb-free package: a = 32-pin tqfp base part number company id: cy = cypress 29946 cy a x t x 51-85063 *c [+] feedback
cy29946 document #: 38-07286 rev. *g page 7 of 9 acronyms document conventions units of measure acronym description esd electrostatic discharge i/o input/output lvcmos low voltage complementary metal oxide semiconductor lvttl low-voltage transistor-transistor logic tqfp thin quad flat pack symbol unit of measure c degree celsius kv kilo volts mhz mega hertz a micro amperes ma milli amperes mm milli meter mv milli volts ns nano seconds ? ohms % percent pf pico farad ps pico seconds vvolts wwatts [+] feedback
cy29946 document #: 38-07286 rev. *g page 8 of 9 document history page document title: cy29946, 2.5 v or 3.3 v, 200-mhz, 1:10 clock distribution buffer document number: 38-07286 rev. ecn no. issue date orig. of change description of change ** 111097 02/07/02 brk new data sheet *a 116780 08/15/02 hwt added the commercial temp erature range in the ordering information *b 122878 12/22/02 rbi added power-up requirements to maximum ratings *c 130007 10/15/03 rgl fixed the block diagram. fixed the mk/oe# description in the pin description table. *d 131375 11/21/03 rgl updated documen t history page (revision *c) to reflect changes that were not listed. *e 221587 see ecn rgl minor change: moved up the word block diagram in the first page. *f 2899714 03/26/10 brij/cxq removed inactive parts from the ordering table. updated package diagram *g 3254185 05/11/2011 cxq added ordering code definitions . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-07286 rev. *g revised may 11, 2011 page 9 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. cy29946 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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